`timescale 1ns / 1ps

//`include "C:/Users/CZH/workspace/riscv_program/riscv_program.srcs/sources_1/new/defines.v"
`include "D:/competiton/innovate-rv/rv_information/hello_led1/hello_led1.srcs/sources_1/new/defines.v"
//`include "D:/competiton/innovate-rv/rv_information/core_risc_v/riscv_program/riscv_program.srcs/sources_1/new/defines.v"
module tb();
    reg clk;
    reg rst;

    riscv u_riscv(
    .clk(clk),
    .rst(rst)
    );

    initial
            begin
            clk = 0;
            rst = 1;

            #50 rst = 0;
            #100 rst = 1;
            end

    always #100 clk = ~clk; 

    initial
        begin
            $readmemh("simple.out", u_riscv.u_inst_ram.ram_);
        end


        

endmodule



 